Over the last several years, DSPs have become an important tool, particularly in the real-time modification of signal streams. They have found use in all manner of electronic devices and will continue to grow in power and popularity.
Those skilled in the art are familiar with DSP architecture in general. Conventional DSPs employ a pipeline through which pass data representing a signal to be processed. An execution core performs various mathematical and logical operations on the data to effect changes therein. Memory is coupled to the execution core. The memory contains not only instructions concerning the way in which the data are to be modified, but also further data that may be employed in conjunction with executing the instructions.
It becomes important at this point to discuss two details with respect to the way in which DSP memory may be architected. First, two fundamental DSP architectures exist that are distinguished from one another by how they interact with memory. So-called “von Neumann” architecture DSPs unify instructions and data in a single memory and a single bus. So-called “Harvard” architecture DSPs split instructions and data between two separate memories and buses and employ separate instruction and data units to load and store to the separate memories via the separate buses. The tradeoff is simplicity (von Neumann) versus speed (Harvard).
Second, more sophisticated DSPs stratify memory in an effort to balance speed, cost and power consumption. In a perfect and simple world, a DSP's memory would be extremely fast, low power, arbitrarily large and on the same physical substrate. Unfortunately, very fast memory is very expensive and requires lots of power and arbitrarily large memory takes an arbitrarily large amount of room on a given substrate. Tempering those requirements with today's commercial concerns regarding both chip and system cost, flexibility and power consumption, modern DSP architecture calls for memory to be stratified, perhaps into three or more layers.
Assuming for the moment that three layers are desired, those might be (1) an extremely small, fast cache, located on the same physical substrate as the processing core of the DSP, that contains very little, but highly relevant instructions or data, (2) a somewhat larger, somewhat slower memory, still located on the same physical substrate as the processing core of the DSP, that contains relevant instructions or data and (3) an external memory that is as large as need be to contain the entirety of a program and data that the DSP is to use, but that is located on a separate physical substrate and accessible only through a comparatively slow external memory interface. It should be noted that processors of all types, including ubiquitous microprocessors, employ the same stratification strategy to balance their speed and cost goals.
Certain tasks that processors may be called upon to perform benefit greatly from the use of “self-modifying code.” A program containing self-modify-ng code changes that code during the program's execution. Self-modifying code turns out to be a powerful programming tool, because the very structure of a particular program can be made to adapt itself dynamically to conditions encountered during the program's execution. John von Neumann, a pioneer in computer science, recognized that computer programs and the data upon which those programs act are indistinguishable from one another, and hence can be stored in the same memory space. This is why the DSP architecture described above that unifies instructions and data in a single memory and a single bus is of a “von Neumann” architecture. In von Neumann architecture DSPs, self-modifying code is straightforward, because the instructions coexist with data, and are therefore readily accessible as though they were data.
However, in a Harvard architecture DSP, instructions are kept in a separate memory from data, and the data unit in the DSP does not have access to the instruction memory. What is needed in the art is an efficient way to accommodate the need for self-modifying code in a Harvard architecture DSP.